What timing constraint do I apply to the automatically-generated altera_reserved_tck clock pin in my design? - What timing constraint do I apply to the automatically-generated altera_reserved_tck clock pin in my design? Description The altera_reserved_tck pin is automatically generated for a design that uses a JTAG accessible module such as the SignalTap™ II logic analyzer, the In-System Memory Content Editor or the Nios® II debugger. To constrain this JTAG clock, apply a 33-MHz clock constraint to this pin. For the TimeQuest Timing Analyzer, use the following command: create_clock -period "30.303 ns" -name {altera_reserved_tck} {altera_reserved_tck} Any datapaths crossing into the altera_reserved_tck clock domain from another domain can be set as false paths. Similarly any datapaths crossing from the altera_reserved_tck domain to another domain can also be set as false paths. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']