Why do I see read, write and erase operation failure when using the OSC_CLK_1 for Intel® Stratix® 10 devices on Macronix flash? - Why do I see read, write and erase operation failure when using the OSC_CLK_1 for Intel® Stratix® 10 devices on Macronix flash? Description You will see the read, write and erase operation failure when the current design runs in the FPGA using OSC_CLK_1 as the configuration clock source on Marconix flash is larger than 128Mb. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.1.1. Custom Fields values: ['novalue'] Troubleshooting 1506956481 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1.1 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['Configuration Devices'] ['novalue'] - 2022-12-13