Address access issues in FPGA CXL Type 1 devices. - Address access issues in FPGA CXL Type 1 devices. Hello， in R-Tile Intel® FPGA IP for Compute Express Link* (CXL*) Design Example, the cust_afu_wrapper accesses the cached host memory in DCOH through the CAFU AXI-MM interface. I would like to ask whether the address in the AXI-MM protocol here should be a physical address or a virtual address? If it is a virtual address, how is it converted into a physical address? Best regards, Mark Replies: Re: Address access issues in FPGA CXL Type 1 devices. Hi, Virtual address is for OS. The FPGA uses physical address. Regards, Rong