The aclr related Recover/Removal timing path should be set false path when you enable the optional reset synchronization in the FIFO parameter editor - The aclr related Recover/Removal timing path should be set false path when you enable the optional reset synchronization in the FIFO parameter editor Description When you use the Quartus® II software v12.1sp1 FIFO parameter editor to generate a DCFIFO and enable the synchronous circuit to synchronize the aclr signal to rclk or wclk by checking the option " Add circuit to synchroniz the 'aclr' input to 'wrclk'/'rdclk '", you might see the recovery and removal timing path from aclr to synchronization registers which are supposed to be cut safely. Resolution Add the following sdc command in the sdc file to cut the related timing path manually: set_false_path -from [get_registers <aclr register name>] -to [get_registers <synchronization registers name>] Custom Fields values: ['novalue'] Troubleshooting 1408185812 False ['FIFO IP'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1.1 ['Arria® V GT FPGA'] ['novalue'] ['novalue'] ['novalue']