Why does the simulation of the GTS Ethernet FPGA Hard IP for the Agilex™ 5 FPGA E-Series Device (Group A), when using System PLL in custom mode, fail with the Quartus® Prime Pro Edition Software version 24.2? - Why does the simulation of the GTS Ethernet FPGA Hard IP for the Agilex™ 5 FPGA E-Series Device (Group A), when using System PLL in custom mode, fail with the Quartus® Prime Pro Edition Software version 24.2? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, the simulation of the GTS Ethernet FPGA Hard IP for the Agilex™ 5 FPGA E-Series Device (Group A) when using System PLL in custom mode fails under the conditions below. Using System PLL in custom mode Reference clock frequency of the GTS Ethernet FPGA Hard IP is 322.265625 MHz Output clock frequency of the GTS Ethernet FPGA Hard IP is configured to 937.5 MHz Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3. Custom Fields values: ['novalue'] Troubleshooting 16023877444 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.2 ['Agilex™ 5 FPGA E-Series'] ['novalue'] ['novalue'] ['novalue']