Error (19169): Transfer between periphery and DSP or RAM will make timing transfer impossible. - Error (19169): Transfer between periphery and DSP or RAM will make timing transfer impossible. Description This error is expected for Intel® Stratix® 10. This is because the Intel® Stratix®10 device only supports transfer to and from the periphery using a core Flip-Flop (FF) and look-up table (LUT). Resolution The workaround is to add the FF or LUT between the periphery. Custom Fields values: ['novalue'] Troubleshooting FB: 448867; HSD: 1408199777 False ['novalue'] ['novalue'] novalue novalue ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']