Missing .dat File Error Message: Failed to open VHDL file - Missing .dat File Error Message: Failed to open VHDL file Description When you simulate a Qsys hardware design in VHDL that contains the JTAG UART core, and you run the simulation using the ld_debug command, you might see the following error message: # ** Error: (vsim-7) Failed to open VHDL file "system_tb_system_inst_jtag_input_stream.dat" in r mode. You can safely ignore this error, because it does not affect the stdout output of the JTAG UART. This error message does not appear when simulating a hardware design in the Verilog HDL. Resolution Run the simulation using the ld command, and the error is not displayed. Alternatively, ignore the error message. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']