How do I map the bit assignment of the TX Parallel Data port of the F-Tile PMA and FEC Direct PHY IP in case of FlexO RS(544, 514) configuration? - How do I map the bit assignment of the TX Parallel Data port of the F-Tile PMA and FEC Direct PHY IP in case of FlexO RS(544, 514) configuration? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1 and earlier, there is no detailed description in the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 15017727234 False ['F-Tile PMA/FEC Direct PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.3.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']