ECC Enabled Automatically in Cyclone V SoC HPS Devices - ECC Enabled Automatically in Cyclone V SoC HPS Devices Description This problem affects DDR2, DDR3, and LPDDR2 products. For HPS hard memory controller interfaces in Cyclone V SoC HPS devices, if you create interface widths of 24 or 40, ECC is enabled automatically, but no message is displayed to state that ECC is enabled. Resolution The workaround for this issue is simply to be aware that ECC is enabled automatically, with no message displayed. This issue will be fixed in a future release. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 13.0.1 ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']