Why is the Fronthaul Compression FPGA IP Example Design unable to meet timing requirements, especially with the Stratix® 10 FPGA H-Tile? - Why is the Fronthaul Compression FPGA IP Example Design unable to meet timing requirements, especially with the Stratix® 10 FPGA H-Tile? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, you may see a timing failure when the Data Direction is set to " TX and RX " and the Compression Method is set to " BFP ". Resolution This problem is fixed in 24.2 release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 15016049394 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 24.1 ['Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 NX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']