Quartus® Prime Software Debug Tools: Signal Tap - This instructor-led class is taught in a virtual classroom in a half day of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera® FPGA Training and pre-configured with all the necessary tools. Information required to connect to the remote system will be provided during the class. No setup is needed. The remote computer connection requires you to be logged in from a PC running either Windows* or macOS* operating systems. Course Description As FPGA designs become more complex, a larger part of development time is spent in design verification. This course introduces and focuses on the Signal Tap embedded logic analyzer, one of the many debug tools included in the Quartus® Prime software. You’ll learn how including the logic analyzer in your FPGA design makes it easy to debug your design quickly by triggering on internal hardware events and monitoring tapped signals, decreasing your overall design development time. You’ll gain experience with using Signal Tap through hands-on lab exercises utilizing the tool in a real design. The class also includes references and links to information about other debugging tools available in the Quartus Prime software, including Signal Probe, In-System Sources & Probes, the Logic Analyzer Interface, and System Console. Course Objectives At course completion, you will be able to: Understand the advantages of using the Signal Tap embedded logic analyzer (ELA) for on-chip debugging Create a Signal Tap file, configure the file, and integrate it into your Quartus Prime software project for debugging a design Make use of additional advanced features of the ELA Skills Required Completion of any introductory Quartus Prime software instructor-led or eLearning course OR a working knowledge of the software If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_IDSW136. FPGA_IDSW136. <p>Quartus Prime Software Debug Tools: Signal Tap</p> - 2025-12-30

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