Why can't I generate the Arria 10 device SerialLite III design example in Quartus Prime Standard editions 16.0, 16.1 and 17.0? - Why can't I generate the Arria 10 device SerialLite III design example in Quartus Prime Standard editions 16.0, 16.1 and 17.0? Description Due to a problem in the Quartus® Prime Standard edition software versions 16.0, 16.1 , and 17.0, you may not be able to generate the Arria® 10 device SerialLite® III design example. The design example generation may hang with the following information in the dialog box: seriallite_iii_a10_0: Generating testbench components for simulation Info: seriallite_iii_a10_0: Generating simulation kick-off scripts Info: seriallite_iii_a10_0: Generating tcl files for QSYS generation Resolution To fix this problem install the Quartus Prime Stratix® V device package. This problem will be fixed in a future version of the Quartus Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 464118; False ['Serial Lite III Streaming IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 17.1 16.0 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']