The HDMI Intel® FPGA IP operating in RX HDMI 2.1 mode does not support FRL rate change initiated by source without hotplug. - The HDMI Intel® FPGA IP operating in RX HDMI 2.1 mode does not support FRL rate change initiated by source without hotplug. Description When a HDMI 2.1 source initiates FRL rate change without hotplug, the HDMI Intel® 2.1 sink cannot link train successfully. This is because HDMI Intel® sink configures the link training pattern to 0x5678 upon a hotplug event or reset. Resolution To work around this problem in the Intel® Quartus® Prime Pro software version 20.4 and earlier, manually hotplug or toggle the 5V detect on the HDMI Intel® FPGA IP sink when the HDMI 2.1 source writes a new FRL rate without hotplug. This problem is fixed starting from version 21.1 of the Intel® Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 1508564354 True ['HDMI IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 19.4 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']