Why are there timing violations within my PLL Reconfig Intel® FPGA IP? - Why are there timing violations within my PLL Reconfig Intel® FPGA IP? Description The maximum frequency for the mgmt_clk and scanclk reconfiguration clock inputs for PLL reconfiguration are specified in the respective device datasheets for Stratix® V, Arria® V, and Cyclone® V devices with the symbol t DYCONFIGCLK . Resolution The PLL Reconfig Intel® FPGA IP might require a lower clock frequency to achieve timing closure. You should use the Timing Analyzer to ensure that your choice of clock frequency for mgmt_clk and/or scanclk will meet the timing requirements of your chosen device. Custom Fields values: ['novalue'] Troubleshooting 1408175663 False ['Avalon ALTPLL'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']