ECC Not Enabled in Cyclone V SoC HPS Devices - ECC Not Enabled in Cyclone V SoC HPS Devices Description This problem affects DDR2, DDR3, and LPDDR2 products. For HPS hard memory controller interfaces in Cyclone V SoC HPS devices, interface widths of 24 (16 plus ECC) and 40 (32 plus ECC) are not supported, because the preloader generator does not enable ECC. Resolution The workaround for this issue is to use non-ECC interface widths of 8, 16, or 32. This issue will be fixed in a future release. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0.1 13.0 ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']