How do I ensure consistent behavior between Avalon-MM and Avalon-ST PCIE HIP in the Stratix V device family? - How do I ensure consistent behavior between Avalon-MM and Avalon-ST PCIE HIP in the Stratix V device family? Description For the Stratix® V device family, to ensure consistent behavior between the Avalon®-MM and Avalon-ST PCI Express® Hard IP, 3 parameters need to be changed from the Avalon-MM wrapper to match the default values in the Avalon-ST wrapper. Resolution In the file altpcie_sv_hip_avmm_hwtcl.v , look for the following parameter definitions near the top of the file (around line 37 and 148) and make the changes identified: parameter deskew_comma_hwtcl = "skp_eieos_deskw", parameter rx_cdc_almost_full_hwtcl = 6, parameter tx_cdc_almost_full_hwtcl = 6, Change to: parameter deskew_comma_hwtcl = "com_deskw", parameter rx_cdc_almost_full_hwtcl = 12, parameter tx_cdc_almost_full_hwtcl = 11, Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']