DDR IP on stratix3 - DDR IP on stratix3 Hi, my project uses stratx3 insides ddr3 controller w/UniPHY, on Fitter lots of 174068 and 174058 errors are appared. Error (174052): I/O "mem_dq[0]" has dynamic termination control connected, but does not use parallel termination that repeats for mem_dq[0] ~ mem_dq[31] mem_dqs[0] ~ mem_dqs[3] mem_dqs_n[0] ~ mem_dqs[3] Error (174068): Output buffer atom "ddr3_ip:U_ddr3_ip|ddr3_ip_0002:ddr3_ip_inst|ddr3_ip_p0:p0|ddr3_ip_p0_memphy:umemphy|ddr3_ip_p0_new_io_pads:uio_pads|ddr3_ip_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_ddio_3reg_stratixiii:altdq_dqs2_inst|obuf_os_0" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination this repeats for dq_ddio[0] ~ dq_ddio[3] approx. 1100 errors in Fitter process. Is there any way to solve this? Replies: Re: DDR IP on stratix3 Hello, Does the errors have been resolved after applying tcl script as mentioned by sstrell? The tcl script should be able to set the IO standard and signal termination for DDR IP. Please let me know if you are still facing the errors. Regards, Adzim Replies: Re: DDR IP on stratix3 IIRC, you had to run a Tcl script to create all the I/O assignments needed to work with the IP. Did you run that script? Found it: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/adding-pins-and-dq-group-assignments.html