Why do I see simulation errors with the GTS CPRI PHY FPGA IP simulation design example when the CDR clock is enabled in the Cadence Xcelium*, the Siemens QuestaFE*, and ModelSim SE* simulators in the Quartus® Prime Pro Edition Software version 24.2? - Why do I see simulation errors with the GTS CPRI PHY FPGA IP simulation design example when the CDR clock is enabled in the Cadence Xcelium*, the Siemens QuestaFE*, and ModelSim SE* simulators in the Quartus® Prime Pro Edition Software version 24.2? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, there are some wrong wire declarations of o_cdr_divclk on the GTS CPRI PHY FPGA IP simulation design example top level; you will see some simulation errors along with some warnings when enabling the GTS CPRI PHY FPGA IP simulation design example with CDR clock enabled, simulation errors occur in tools such as the Cadence Xcelium*, the Siemens QuestaFE* and ModelSim SE* simulators. Resolution This problem is fixed in 24.3 release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 15016577506 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] 24.3 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']