Why might I see de-asserted tx_pll_locked or tx_ready signals with my Agilex™ 7 FPGA transceiver F-Tile design when using the Quartus® Prime Pro Edition Software versions 23.1 and earlier? - Why might I see de-asserted tx_pll_locked or tx_ready signals with my Agilex™ 7 FPGA transceiver F-Tile design when using the Quartus® Prime Pro Edition Software versions 23.1 and earlier? Description Due to a bug in the Quartus® Prime Pro Edition Software versions 23.1 and earlier, some F-Tile transmitters may remain in reset, which results in the tx_pll_locked or tx_ready signals being permanently de-asserted. This intermittent problem may be seen with some Quartus® Prime Pro Edition Software compiled project programming files but not others. It only affects Quartus® Prime Pro Edition Software designs that use more than one Agilex™ 7 FPGA F-Tile. Resolution To fix this problem in the Quartus® Prime Pro Edition Software versions 22.4 and 23.1, install the following patches: Patch 0.33 for Quartus Prime Pro Edition Software version 22.4 Patch 0.17 for Quartus Prime Pro Edition Software version 23.1 To fix this problem in the Quartus® Prime Pro Edition Software versions 22.3 and earlier, you must upgrade your design to Quartus® Prime Pro Edition Software version 22.4 or 23.1 and install the corresponding patch. This problem will be fixed in a future revision of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18028546007 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']