** Warning nofile(37) in protected region. - ** Warning nofile(37) in protected region. Description You may experience the above warning while simulating a VHDL-based DDR3 UniPHY memory controller with ModelSim. When the DDR3 memory controller is generated in VHDL, all Verilog and SystemVerilog submodules are encrypted to allow simulation with a single-language simulator. If a warning occurs in the encrypted fileset, a cryptic message like the one above will be generated. Resolution Make sure the DDR3 files are being compiled in the order specified in the msim_setup.tcl file in the <variation_name>_sim directory. Any files compiled out-of-order may result in the above warning. If you still see the above warning after compiling the files in the correct order, you will need to create a Verilog-based DDR3 UniPHY memory controller and use the unencrypted Verilog and SystemVerilog files in place of the encrypted fileset to isolate the source of the warning. This requires a dual-language simulator like ModelSim SE. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Simulation'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']