How do I simulate Verilog HDL files generated from schematic designs? - How do I simulate Verilog HDL files generated from schematic designs? Description Due to a problem in the Quartus® II software version 12.1 SP1 and earlier, Verilog HDL files generated from schematic block design files ( .bdf ) may not simulate correctly. This problem occurs when schematic designs contain Altera® primitives. Verilog HDL files generated from schematics refer to these primitives using all upper-case letters. Verilog HDL simulation libraries for these primitives use all lower-case letters. For example, Verilog HDL files generated from schematics may include the module SRFF , while the simulation libraries include the module srff . Resolution To work around this problem, edit any Verilog HDL files created from schematic designs and change references to Altera primitives from all upper-case to all lower-case letters. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 9.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']