Is there an known issue with the Arria 10 EDCRC Clock Divisor setting? - Is there an known issue with the Arria 10 EDCRC Clock Divisor setting? Description In Quartus ® Prime software version 16.0 and earlier, when the "Enable Internal Scrubbing" option is turned on without enabling the CRC ERROR pin option for Arria ® 10 devices, the EDCRC clock divider value will default to 4 regardless of user selection from the dropdown list. Resolution This problem is scheduled to be fixed in a future version of the Quartus Prime software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 15.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']