rx_oc_busy Port Is Not A Top-Level Signal - rx_oc_busy Port Is Not A Top-Level Signal
Description The 10GBase-R PHY IP Core chapter of the Altera Transceiver PHY IP Core User Guide describes the rx_oc_busy signal as a top-level signal of the IP core; however, this signal is now included in the reconfiguration bus. Resolution This issue is fixed in version 11.1 SP2 of the Altera Transceiver PHY IP Core User Guide .
Custom Fields values:
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Troubleshooting
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True
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['FPGA Dev Tools Quartus II Software']
11.1.2
11.0
['Programmable Logic Devices']
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['novalue'] - 2021-08-25
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