Link Training Issues when Using the ATX PLL and Soft Reset Controller with Gen2 Arria V GZ Hard IP for PCI Express IP Core - Link Training Issues when Using the ATX PLL and Soft Reset Controller with Gen2 Arria V GZ Hard IP for PCI Express IP Core Description If you use the ATX PLL and soft reset controller with a Gen2 Arria V GZ Hard IP for PCI Express IP Core, you may observe link training speed changes issues. This issue occurs because this configuration incorrectly uses hard offset cancellation at startup instead of soft offset cancellation. Resolution The workaround is to select the CMU PLL and the hard reset controller for Gen2 variants of the Arria V GZ Hard IP for PCI Express IP Core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1 ['Arria® V GZ FPGA'] ['novalue'] ['novalue'] ['novalue']