Why is the Control Status Register(CSR) latency inconsistent during back-to-back interleaved reads between TX and RX statistics counter in the Triple-Speed Ethernet Intel® FPGA IP operating in 10Mbps speed mode? - Why is the Control Status Register(CSR) latency inconsistent during back-to-back interleaved reads between TX and RX statistics counter in the Triple-Speed Ethernet Intel® FPGA IP operating in 10Mbps speed mode? Description Due to a problem in the Intel® Quartus® Prime Software version 19.1 and 19.2, inconsistent CSR latency will be observed during back-to-back interleaved reads between TX and RX statistics counters in the Triple-Speed Ethernet Intel® FPGA IP operating in 10Mbps speed mode. Resolution To work around this problem, add interval of more than 1300ns between any Tx path statistics counter read to Rx path statistics counter read. This problem has been fixed starting in the Intel® Quartus® Prime Pro Software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1507279766 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 19.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']