Why is the SPT/CPB block content erased when using the Mailbox Client Intel® FPGA IP in Intel® Stratix® 10 or all Intel Agilex® devices to execute the QSPI_ERASE command to erase and update the P1 partition or Application Image 1? - Why is the SPT/CPB block content erased when using the Mailbox Client Intel® FPGA IP in Intel® Stratix® 10 or all Intel Agilex® devices to execute the QSPI_ERASE command to erase and update the P1 partition or Application Image 1? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software starting from version 19.3 and above, when the start address of the P1 partition or Application Image 1 is manually assigned by the user, the Programing File Generator tool will assign the Sub-partition table (SPT) or pointer block (CPB) contents in the same flash sector (64 KB) with the P1 partition or Application Image 1. Therefore, the content of the SPT/CPB block will be erased when using the Mailbox Client Intel® FPGA IP in Intel® Stratix® 10 or Intel Agilex® devices to execute the QSPI_ERASE command to erase and update the P1 partition or Application Image 1. Resolution To work around this, add 32 KB padding to the factory image. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16012327698 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 19.3 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']