How can I reduce the Partial Reconfiguration (PR) bitstream file size in the Intel® Stratix® 10 and Intel Agilex® FPGA devices? - How can I reduce the Partial Reconfiguration (PR) bitstream file size in the Intel® Stratix® 10 and Intel Agilex® FPGA devices? Description The size of the PR bitstream file for the Intel® Stratix® 10 and Intel Agilex® FPGA devices is dependent on the number of clock sectors covered by the PR region. A larger number of clock sectors covered by the PR region results in a larger bitstream file size. Consequently, PR programming time will increase accordingly. Resolution To reduce PR bitstream file size, follow the two tips below: Target only the necessary number of clock sectors for PR region. When aligning the Routing Region to clock sectors, ensure that the Routing Region is one LAB row/column inset from the edge of clock sector boundaries. Custom Fields values: ['novalue'] Troubleshooting 16015324342 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.1 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']