Why does the o_p0_rx_hi_ber port of the F-Tile Ethernet Multirate FPGA IP assert following the AN/LT and DR from the 100GE-4 to the 2x50GE-1 profile when simulating the F-Tile Dynamic Reconfiguration Suite FPGA IP Design Example? - Why does the o_p0_rx_hi_ber port of the F-Tile Ethernet Multirate FPGA IP assert following the AN/LT and DR from the 100GE-4 to the 2x50GE-1 profile when simulating the F-Tile Dynamic Reconfiguration Suite FPGA IP Design Example? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and newer, the o_p0_rx_hi_ber port of the F-Tile Ethernet Multirate FPGA IP can assert following the Auto-negotiation and link training (AN/LT) and Dynamic Reconfiguration(DR) from the 100GE-4 profile to the 2x50GE-1 profile in simulation of the F-Tile Dynamic Reconfiguration Suite FPGA IP Design Example. This problem does not affect the Design Example in hardware. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.2. Custom Fields values: ['novalue'] Troubleshooting 14021883951 False ['F-Tile Dynamic Reconfiguration Suite IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']