Why does the GTS HDMI FPGA IP Design Example fail on hardware? - Why does the GTS HDMI FPGA IP Design Example fail on hardware? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1, the GTS HDMI FPGA IP Design Example fails to link after programming. This is due to the Input Reference Clock Buffer Protection enablement; the clock buffers are turned off before device configuration starts and never turned back on even when the reference clock becomes available. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.3.1. Download and install Patch 1.02fw from the following links: quartus-24.3.1-1.02fw-windows.exe quartus-24.3.1-1.02fw-linux.run Readme for version 24.3.1 Patch 1.02fw (.txt) This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15017386064 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.3.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']