Why do I see hold timing violations within Altera DDR3 IP on paths where both the source and destination register are placed within a single ALM? - Why do I see hold timing violations within Altera DDR3 IP on paths where both the source and destination register are placed within a single ALM? Description Due to a problem in the Quartus® II software versions 13.0 SP1 and earlier, you may see hold timing violations in your Altera DDR3 IP for paths where both the source and destination register are placed within a single ALM. The problem occurs due to a placement and routing limitation which is specific to the DDR3 IP. Resolution To avoid this problem, comment out (using #) all of the automatically-generated FORM_DDR_CLUSTERING_CLIQUE assignments from the project Quartus II Settings File ( .qsf ). This problem is scheduled to be fixed in a future release of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']