Why is my calculated value for Tx or Rx UI incorrect when using the scripts found in the design examples for Precision Time Protocol (PTP) variants of the F-Tile Ethernet Intel® FPGA Hard IP? - Why is my calculated value for Tx or Rx UI incorrect when using the scripts found in the design examples for Precision Time Protocol (PTP) variants of the F-Tile Ethernet Intel® FPGA Hard IP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, the scripts provided in the F-Tile Ethernet Intel® FPGA Hard IP Designs with Precision Time Protocol (PTP) can show incorrect Tx or Rx UI values. Resolution To work around this problem, perform the following steps : Open the PTP firmware script located at <generated example design folder>/hardware_test_design/hwtest/altera/ptp/ptp_fw.tcl Find and replace the following lines of code: FROM set tx_tam_cnt [format 0x%X [expr [expr $rd_data & 0x 3 FFF0000] >> 16]] TO set tx_tam_cnt [format 0x%X [expr [expr $rd_data & 0x 7 FFF0000] >> 16]] FROM set rx_tam_cnt [format 0x%X [expr [expr $rd_data & 0x 3 FFF0000] >> 16]] TO set rx_tam_cnt [format 0x%X [expr [expr $rd_data & 0x 7 FFF0000] >> 16] FROM set tx_tam_cnt_delta_max 3276 7 TO set tx_tam_cnt_delta_max 3276 8 FROM set rx_tam_cnt_delta_max 3276 7 TO set rx_tam_cnt_delta_max 3276 8 Save the file This problem has been fixed starting in version 22.3 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 15011582861 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 22.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']