Why does the Low Latency 100G Ethernet Stratix® 10 FPGA IP show 'H-Tile' as 'Target transceiver tile' when targeting a 'L-Tile' only device? - Why does the Low Latency 100G Ethernet Stratix® 10 FPGA IP show 'H-Tile' as 'Target transceiver tile' when targeting a 'L-Tile' only device? Description When working with a 'L-Tile' only device, the 'Target transceiver tile' drop down menu is disabled and shows the 'H-Tile' default value. 'H-Tile' is coded in the component description file as its default. Resolution The designer can safely ignore the 'H-Tile' as 'Target transceiver tile' when targetting L-Tile devices, the IP will generate HDL targeting the correct device tile. This problem will be fixed in a future release of the Quartus® Prime Software. Custom Fields values: ['novalue'] Troubleshooting FB: 596245; False ['Low Latency 100G Ethernet IP for Arria® 10 and Stratix® V'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.1 18.1 ['Stratix® 10 FPGAs and SoCs', 'Stratix® 10 GX FPGA', 'Stratix® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']