Hard IP for PCI Express Synthesis Does Not Support Third-Party EDA Synthesis Tools - Hard IP for PCI Express Synthesis Does Not Support Third-Party EDA Synthesis Tools Description The Qsys Generate HDL Synthesis menu allows you to choose Create timing and resource estimates for third-party EDA synthesis tools . However, this option is not available for the Hard IP for PCI Express IP cores. Resolution Do not select the Create timing and resource estimates for third-party EDA synthesis tools option when generating synthesis files for any variant of the Hard IP for PCI Express. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PCI Express'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']