Agilex 7 and Stratix 10 FPGA E-Tile Hard IP - The Agilex 7 and Stratix 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible with the IEEE 802.3 High-Speed Ethernet Standard and the 25G and 50G Ethernet… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 TX FPGA The Agilex 7 and Stratix 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible with the IEEE 802.3 High-Speed Ethernet Standard and the 25G and 50G Ethernet Specification, Draft 1.6 from the 25G Ethernet Consortium. The Intellectual Property (IP) core provides access to this hard IP at data rates of 10 Gbps, 25 Gbps, and 100 Gbps. The MAC provides cut-through frame processing to optimize latency and supports full wire line speed with a 64-byte frame length and back-to-back or mixed-length traffic with no dropped packets. All IP core variations are in full-duplex mode. This IP core is available in multiple variants, each providing a different combination of Ethernet channels and features: 1) One to four 10GbE/25GbE channels with optional Reed-Solomon Forward Error Correction (RS-FEC). 2) 100G channel with optional RS-FEC for either CAUI-4 or CAUI-2 mode. 3) Dynamic configuration between one to four single 10GE/25GE channels or one 100GE channel; All the variants provide an optional IEEE 1588v2 Precision Time Protocol (PTP). The user can choose a media access control (MAC) and a physical coding sublayer (PCS) variation, a PCS-only variation, a Flexible Ethernet (FlexE) variation, or an Optical Transport Network (OTN) variation. Ethernet Access Aerospace ASIC Proto Broadcast Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless Agilex 7 and Stratix 10 FPGA E-Tile Hard IP Key Features The PHY supports: 1) CAUI external interface consisting of four FPGA hard serial transceiver lanes operating at 25.78125 Gbps. CAUI-2 external interface with two transceiver lanes operating at 53.125 Gbps with PAM4 encoding. 2) CAUI-4 links based on 64B/66B encoding with data striping and alignment markers to align data from multiple lanes. 3) Optional Reed-Solomon Forward Error Correction RS-FEC (528,514) or RS-FEC (544,514). 4) 10G, 25G, and 100G variations. 5) Auto-Negotiation (AN) and Link Training (LT) Offering Brief No No No Yes Encrypted Verilog Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 TX FPGA Yes Yes Offering Brief Production a1JUi0000049UUvMAM What's Included Encrypted Verilog source code Ordering Information IP-ETH-ETILEHIP; IP-ETH-ETILEKRCR Direct a1JUi0000049UUvMAM Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2025-08-28T18:42:48.000+0000 The Agilex 7 and Stratix 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible with the IEEE 802.3 High-Speed Ethernet Standard and the 25G and 50G Ethernet Specification, Draft 1.6 from the 25G Ethernet Consortium. The Intellectual Property (IP) core provides access to this hard IP at data rates of 10 Gbps, 25 Gbps, and 100 Gbps. Altera Solutions