** Warning: ../ip_ad_lvds/altera_lvds_core14_181/sim/ip_ad_lvds_altera_lvds_core14_181_ibrwinq.sv(1): (vlog13233) Design unit "ip_ad_lvds_altera_lvds_core14_181_ibrwinq" already exists and will be overwritten. - ** Warning: ../ip_ad_lvds/altera_lvds_core14_181/sim/ip_ad_lvds_altera_lvds_core14_181_ibrwinq.sv(1): (vlog13233) Design unit "ip_ad_lvds_altera_lvds_core14_181_ibrwinq" already exists and will be overwritten.
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.1, you may see the following warning (as shown below) in the ModelSim* GUI when using Intel® Stratix® 10 LVDS SERDES IP: ** Warning: ../ip_ad_lvds/altera_lvds_core14_181/sim/ip_ad_lvds_altera_lvds_core14_181_ibrwinq.sv(1): (vlog13233) Design unit "ip_ad_lvds_altera_lvds_core14_181_ibrwinq" already exists and will be overwritten. Overwriting a VHDL entity with a Verilog module. Resolution There is no workaround for this issue. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.
Custom Fields values:
['novalue']
Troubleshooting
2205699867
False
['I O']
['FPGA Dev Tools Quartus® Prime Software Pro']
19.3
19.1
['Stratix® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2023-01-20
external_document