Why does the F-Tile Serial Lite IV Toolkit fail to enable Internal Serial Loopback during Link Initialization? - Why does the F-Tile Serial Lite IV Toolkit fail to enable Internal Serial Loopback during Link Initialization? Description There is a problem with the F-Tile Serial Lite IV Toolkit. Internal serial loopback enablement is unsuccessful and outputs an incorrect register value when performing Link Initialization. It's because we internally changed to demo_jtag when checking the tx_pll_locked and rx_cdr_locked status during the system-reset proc, but didn't change it back to phy_jtag when completed. Resolution To work around this problem, you need to follow the steps below: Click "Assert system Reset" Click "Deassert system Reset" Go to GUI Configuration tab and set JTAG to phy_jtag_m.master Click "Link Initialization" This has been fixed in Quartus® Prime Pro 24.3. Custom Fields values: ['novalue'] Troubleshooting 15015884922 False ['Serial Lite IV IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']