Power Analysis & Optimization for Altera® Arria 10 & Stratix 10 Devices: Optimization - 51 Minutes This is part 3 of 4. Designing for low-power in today’s high-speed Altera® Stratix® 10 and Arria® 10 FPGA designs is more important than ever. Knowing the final design’s power usage early in the design process is necessary for making power supply and device cooling decisions. This training will give you the knowledge and tools you need to perform highly accurate estimates of power usage and what to do to optimize power. In this third part, you'll learn many different techniques for optimizing a design for power, from simple settings adjustments to perform a power-driven compilation in the Altera® Quartus Prime software, to making design changes that affect how the design gets compiled. Course Objectives At course completion, you will be able to: Analyze and optimize power usage in all stages of the FPGA design process for Altera® Arria® 10 and Altera® Stratix® 10 devices Understand the differences between static and dynamic power and how they are analyzed by the tools Optimize power by performing a power-driven compilation and by following low-power design guidelines Skills Required Completion of “Using the Quartus Prime Software: An Introduction” OR a basic understanding of the FPGA design flow and the Altera® Quartus Prime software Basic understanding of timing analysis Basic knowledge of performing simulations in 3rd-party EDA simulation tools If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OPWRA10S103. FPGA_OPWRA10S103. <p>Power Analysis & Optimization for Altera Arria 10 & Stratix 10 Devices: Optimization</p>