Why does simulation fail for the RapidIO II Megacore when using VHDL? - Why does simulation fail for the RapidIO II Megacore when using VHDL? Description Due to a problem with the Quartus® II software, simulation will fail for the RapidIO II Megacore when the simulation model is generated using VHDL. Resolution You must use the Verilog simulation model. This problem is scheduled to be fixed in a future version of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']