Error (12418): Termination logic option is set to Differential for input pin xxx/io_iobuf_2_n, but setting is not supported by I/O standard I/O standard 1.2-V - Error (12418): Termination logic option is set to Differential for input pin xxx/io_iobuf_2_n, but setting is not supported by I/O standard I/O standard 1.2-V Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 and earlier, you might see this error when generating an LVDS example design with the I/O standard set to SLVS 1.2V in RX mode. This error only occurs when targeting Agilex™ 5 devices. Resolution To workaround this problem, reassign the channel to a pin other than "0405" in the "Pin Setting" tab before generating the example design. This problem is fixed begining with the Quartus® Prime Pro Edition Software version 24.3. Custom Fields values: ['novalue'] Troubleshooting 15016757651 False ['LVDS SERDES IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']