Why are there minimum pulse width timing violations in Fault Injection IP for Cyclone® V device with the Quartus® II software version 15.0 Update 2 ? - Why are there minimum pulse width timing violations in Fault Injection IP for Cyclone® V device with the Quartus® II software version 15.0 Update 2 ? Description Due to a problem in the Quartus® II software version 15.0 Update 2, when the Single Event Upset(SEU) feature is implemented in the Cyclone® V device with the following clock constraint, you may find minimum pulse width timing violations for some signals in Fault Injection IP. create_clock -name intosc -period 10.000 [get_nets {*fault_injection_0|alt_fault_injection_component|alt_fi_inst|intosc}] Resolution The problem is fixed beginning with the Intel® Quartus® Prime Standard Edition software version 16.0r. Custom Fields values: ['novalue'] Troubleshooting 1409085640 False ['Fault Injection IP'] ['FPGA Dev Tools Quartus II Software'] 16.0 15.0.2 ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']