Why is my HPS DDR3 controller failing calibration? - Why is my HPS DDR3 controller failing calibration? Description Your HPS DDR3 controller generated with Quartus® II software version 13.0 or 13.0sp1 may experience a calibration failure and produce the following debug messages in the debug output text file: test_load_patterns(0,ALL) => (85 == 255) => 0 Guaranteed read test failed SEQ.C: Calibration Failed SEQ.C: Error Stage : 1 SEQ.C: Error Substage: 1 SEQ.C: Error Group : 0 There is a known issue where the HPS Vref pins draw high current causing the Vref voltage to drop and DDR3 calibration to fail. Resolution Install the Quartus® II 13.0SP1 release DP5 patch. See the link in Related Solutions below. The same fix is also available as a separate patch (1.34) for the Quartus® II 13.0SP1 release. It is recommended that users install the DP5 patch, but should a separate patch for only the HPS Vref issue be required, please contact Altera. This issue has been fixed in the Quartus® II software 13.1 release. Related Articles How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 13.0 SP1? Why is the Cyclone V SoC Device SDRAM interface Vref pin voltage incorrect ? Custom Fields values: ['novalue'] Troubleshooting 1408032347 False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] 13.1 13.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']