Why can the PLL not be instantiated when using PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP? - Why can the PLL not be instantiated when using PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1, the phase-locked loop (PLL) cannot be instantiated on the top sub-bank when using PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP. Resolution To work around this problem, the differential reference clock input can be instantiated in the bottom sub-bank at a pin index of 34-35 or 36-37. While a single reference clock input can only be instantiated in the bottom sub-bank at a pin index of 34 or 36. If you need to instantiate the reference clock input in the top sub-bank, you have to add the following assignment to the Quartus® Prime Pro Edition Software Settings File ( .qsf ): set_intance_assignment -name PLL_REFCLK_INPUT_TYPE NOT_BALANCED -to *arch_inst|phylite_clocking_inst|iopll_inst This problem is fixed starting with the Quartus® Prime Pro Edition Software version 23.2. Custom Fields values: ['novalue'] Errata 22016625652 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 23.1 ['Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']