Why does my multi-instance design example for the F-tile Ethernet Intel® FPGA Hard IP fail to achieve link on an intermittent basis? - Why does my multi-instance design example for the F-tile Ethernet Intel® FPGA Hard IP fail to achieve link on an intermittent basis? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, the reset logic for the multi-instance design example for the F-tile Ethernet Intel® FPGA Hard IP is improperly implemented. This leads to intermittent link failures upon initial bring-up of the design example. This problem exists for all multi-instance design examples, regardless of IP variant. Resolution To work around this problem, perform the following steps: Navigate to the <design example name>/hardware_test_design/ directory. Open the eth_f_hw.v file. This is the top level of the design example. Change the following line: FROM: assign rst_n[i] = arst; TO: assign rst_n[i] = source_rst_n; Compile the design example. This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.4. Custom Fields values: ['novalue'] Troubleshooting 18024185289 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 22.2 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']