DDR2 and DDR3 SDRAM Controller with UniPHY User Guide Contains Incorrect Clock Information - DDR2 and DDR3 SDRAM Controller with UniPHY User Guide Contains Incorrect Clock Information Description In the user guide, table 6-1 contains incorrect clock phase information for pll_mem_clk and pll_write_clk .Also, table 6-2 is inapplicable and should be ignored. Resolution The correct phase for pll_mem_clk is 0° for interfaces with the Leveling Interface� Mode set to Leveling , and -45° for interfaces with Leveling Interface Mode set to Nonleveling .�The correct phase for pll_write_clk is 90° for interfaces with the Leveling Interface� Mode set to Leveling , and -135° for interfaces with Leveling Interface Mode set to Non-leveling . Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.1 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']