Why does simulation of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* example design testbench not include a DMA process? - Why does simulation of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* example design testbench not include a DMA process? Description Due to a problem with the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* example design testbench DMA transactions are not processed. Resolution In current versions of the Intel® Quartus® Prime Design Software, to correctly simulate DMA processes, modify the ' apps_type_hwtcl ' parameter from ' 3 ' to ' 6 ' within the ' altpcie_a10_tbed_hwtcl ' module instantiation in the file ' dut_pcie_tb_ip.v '. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4. Custom Fields values: ['novalue'] Troubleshooting 1509686040 False ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.4 21.2 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']