Why doesn't assertion of the pll_powerdown input signal reset the Intel® Arria® 10 device fPLL? - Why doesn't assertion of the pll_powerdown input signal reset the Intel® Arria® 10 device fPLL? Description By default, the Intel® Arria® 10 fPLL IP core's internal reset signal is controlled by the Avalon-MM register but not the pll_powerdown input signal. Therefore, asserting the pll_powerdown input signal will not reset the Intel® Arria® 10 fPLL. Resolution Add the following QSF assignment to change the reset control from the Avalon-MM register to the pll_powerdown input: set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS=1" Custom Fields values: ['novalue'] Troubleshooting 1507661696, 1507719020 False ['fPLL Arria® 10 Cyclone® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 19.3 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']