Active-High Reset Even If You Select Active Low Reset - Active-High Reset Even If You Select Active Low Reset Description Some blocks continue to use active-high reset, even if you select active-low reset..This issue affects all designs that use the following blocks: List ForLoop The design fails Resolution To work around the issue, do not select active-low reset. This problem is fixed in DSP Builder v13.1. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']