Why is my Intel® Arria® 10 FPGA DDR4 design failing compilation in the fitter when I choose "Automatically select a location" for ALERT# pin placement? - Why is my Intel® Arria® 10 FPGA DDR4 design failing compilation in the fitter when I choose "Automatically select a location" for ALERT# pin placement? Description If the " Automatically select a locatio n" option is chosen in the Memory Topology/ Topology tab of the Intel® Arria® 10 FPGA DDR4 IP Editor, the IP will automatically choose a pin assignment for the mem_alert_n signal. If this option is selected and conflicting location constraints are applied to the mem_alert_n pin, fitter errors will result during compilation. The fitter errors will include these messages: Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action. Resolution If you use the " Automatically select a location " option, remove all location assignments and constraints for the mem_alert_n signal in your .QSF file. Intel recommends manually placing the mem_alert_n signal in the address/command bank for optimum timing margins by choosing the " I/O Lane with Address/Command Pins " option. Custom Fields values: ['novalue'] Troubleshooting FB: 419530; False ['External Memory Interfaces Arria® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software QUARTUS-ALITE', 'FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 16.0.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']