Why does the Intel® Arria 10® PCI Express* Hard IP lane error status register fail to clear? - Why does the Intel® Arria 10® PCI Express* Hard IP lane error status register fail to clear? Description Due to a problem with the write address decoding for the Intel® Arria® 10 PCI Express* Hard IP, you may fail to clear the lane error status register after writing ‘1’ to this register. Resolution To work around this problem, write a ‘1’ to link control 3 registers (Offset 04h) located in the Secondary PCI Express* Extended Capability. This register will be set, and the lane error status register will be cleared. Custom Fields values: ['novalue'] Troubleshooting FB: 588930; True ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']