Why do I get an error when simulating the R-Tile Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example using the VCS simulator? - Why do I get an error when simulating the R-Tile Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example using the VCS simulator? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4, an error will be observed when trying to simulate the R-Tile Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example for Intel Agilex® devices using the VCS simulator. The following error message will be seen: INFO: 497636 ns Starting DMA Read....H2D INFO: 500949 ns Queue Reset...done INFO: 501149 ns Waiting for MSI-X Writeback for Read DMA........ FATAL: 4000000 ns Simulation stopped due to inactivity! FAILURE: Simulation stopped due to Fatal error! FAILURE: Simulation stopped due to error! $finish called from file "./../..//../../ip/pcie_ed_tb/dut_pcie_tb_ip/intel_rtile_pcie_tbed_100/sim/altpcietb_g3bfm_log.v", line 144. Resolution There is no workaround for this problem. This problem has been fixed starting with version 23.1 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 22016466902 False ['Multi Channel DMA for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']